The present invention relates to a pipeline type A/D converter, and particularly to a pipeline type A/D converter having multi-bit pipeline stages.
With the development of a system LSI technology in recent years, it became possible to mount a large scale system onto one LSI. A data converter used for the input/output of an analog signal becomes absolutely essential for such a system LSI. Particularly since an A/D converter employed in the system LSI has frequently been inputted with a plurality of various information such as signals and image signals from a sensor and wireless or radio signals, it is not uncommon that a plurality of A/D converters are mounted onto the system LSI.
When the plural A/D converters are mounted on the system LSI, a pipeline A/D converter has recently been used frequently from the need to place the same on a limited area. This pipeline A/D converter is excellent in not only an exclusive area but also power consumption. Further, a reduction in the area and low power consumption have been required therefor. A pipeline type A/D converter (called also “multi-bit pipeline type A/D converter”) having multi-bit pipeline stages has been researched and developed as shown in a non-patent document 1 (Study of Multi-Bit Pipeline Type A/DC (Endo et al., Institute of Electronics, Information and Communication Engineers, 2006, ICD)).
The multi-bit pipeline type A/D converter is an extension of the conventionally well-known 1.5-bit type pipeline and is equivalent to one in which an arithmetic operation of each pipeline stage is expanded from 1 bit to plural bits. The pipeline type A/D converter has advantages in that since the number of bits per stage is large, the number of stages can be reduced, and a shift or displacement in stage gain that has become a problem upon a pipeline configuration like the influence of a capacitance mismatch and the like can be reduced.